1.0 Overall Description
 

The bias electronics subsystem of the ALMA Evaluation Receiver provides DC bias, control and monitoring of the front end electronics. Physically, the system consists of a rack module, which contains the majority of the electronics, and electronic subassemblies integrated into the receiver cartridges. Each is described in detail in the following sections. A block diagram of the overall system is shown in Figure 1.
 

Appendix A contains lists of all archived drawings and documents relevant to the bias subsystem. The electronic (HTML) version of this document includes hyperlinks in this appendix to the latest source files, for download. Otherwise, versions current with this document release can be viewed in Adobe PDF format by accessing the links in the relevant sections below.
 
 
 

2.0 Bias Electronics in the Receiver Cartridges
 

Most of the bias electronics for components within the receiver cartridges is located in the Electronics Bin. However, the bias circuit for the SIS mixer and passive protection circuits for the InP amplifiers are integrated into assemblies that bolt directly onto the cartridge. Each of these electronic subassemblies (called Filtered Feedthru Assemblies, or FFTAs) are installed into the cartridge base. There are two basic types, one with an SIS bias card, the other with an InP LNA protection circuit (schematics). In each, the board is mounted vertically on a dual row, 24-pin hermetic filtered feedthru plate, which is connectorized on the ambient side. All DC connections into the cartridge (including the temperature sensor leads) pass through the FFTAs.
 

The SIS bias and LNA protection electronics are located within the vacuum space of the dewar. While this may have drawbacks (potential outgassing, warmup required for board replacement), there are a number of advantages, namely:
 

• No need for a board enclosure; vacuum dewar also provides good EMI shield.
• Better isolation/protection of SIS mixers from EMI, ESD.
• Reduces space needed below the cartridge wall.

 

2.1 Dual SIS Mixer Bias Card
 

The ALMA Dual SIS Mixer Bias card (schematic : parts list) provides programmable DC bias for two independent SIS mixers, along with analog monitor outputs of mixer voltage and current. It is evolved from an earlier single-mixer design by Kerr (NRAO-Charlottesville), and is compatible with the 6-wire NRAO Type II-B SIS bias tee [1]. While the bias circuit design retains nearly the same monitor feedback servo loop to stabilize the bias voltage, many changes were made for use on ALMA receivers:
 

• Open-loop mode was eliminated. This was not deemed essential for a receiver in the field, and significantly reduced the component count. The I-V curves of the SIS mixers can be taken a point at a time via the monitor and control system, with the bias servo loop closed.

• Null pots were eliminated. This was done to enhance reliability, save space and eliminate manual calibration, allowing it to be installed directly on or within the receiver cartridge. A non-nulled, precision instrumentation amp with lower drift, noise and comparable or better input offset performance was selected (LT1167A). The residual offsets in the bias voltage and current monitors are small, relative to the nominal mixer bias point, and are unimportant in tuning the mixers for optimum noise. Nevertheless, these offsets can be measured on the bench, and the values stored and used to correct the monitor data, effectively "zeroing" the circuit in software.

 
• The mechanical rotary protection switch was eliminated. Because the bias card is to be integrated within the receiver cartridge, an external mechanical switch was deemed unnecessary and impractical for the array. This also saves a substantial amount of space and wiring complexity. To protect the SIS mixer from excessive input voltage (due to a circuit failure or transient spikes on the board inputs), a bidirectional diode clamp was added to limit the drive output to within a safe level. The diodes are electrically equivalent to a 1N4448, but in a very small surface mount package (MicroMELF), to save board space.

 
• SIS driver (op-amp buffer) was replaced with instrument amp. Because the instrument amplifier includes a remote output reference terminal, connecting the S- (return) lead from the mixer block to this pin subtracts out any induced noise voltage at the mixer local ground, relative to the bias circuit ground. Note: It is still necessary to have a relatively low resistance connection (< 10 ohms) between the SIS mixer block and earth/supply ground, in order for the bias circuit control loop to function properly.

 
• All manual bias control (via pots) was eliminated. Again, this was not deemed necessary for a receiver in the field, and saved board space.

 
• ESD protection was added on all monitor and control and power inputs. This enhances protection of the mixers and the bias circuitry from electrostatic discharge (ESD) or other transients, during normal operation of the receiver, servicing, or handling/transport of the receiver cartridge. Note: For full bipolar biasing of mixers, these must be removed.

 
• The supply voltage to the devices was lowered to ±5V. This was done primarily to lower power dissipation on the board, for operation in a vacuum. A secondary reason was the broader availability of ultra-compact, low-noise voltage regulators in this range. The scaling of the monitor outputs was adjusted to accommodate this smaller available output swing.

 

A differential analog input (0 to 4V) on each mixer bias circuit sets the mixer voltage (0 to 20mV). Buffered monitors of the SIS junction voltage and current on each mixer are provided, for a total of four monitor outputs. Details on monitor and control of the card are covered in the programming section of this document.
 

With the exception of the integrating capacitors, all components are surface mount, with a multilayer PCB populated on both sides. Extremely small, space-qualified connectors were used at the interface to the cartridge wiring, drastically reducing the board size over standard connectors. The resulting circuit is extremely compact (38 x 63 mm) and easily fits inside the dewar.
 

The photo in Figure 3 shows the top and bottom views of the bias board. Two 9-pin connectors (left side, top) connect to each of the mixers, while the 15-pin connector between them is for mixer magnet bias and temperature sensor leads, which pass through the board.
 

2.2 InP LNA Protection Board
 

The ALMA InP LNA Protection board (schematic : parts list) provides overvoltage, transient and reverse polarity protection for both gate and drain terminals of six (6) InP HEMT devices. The protection circuit design is identical to one developed at the NRAO-CDL for use with InP LNAs, except it has been miniaturized through use of surface-mount components.
 

Figure 4 shows a photograph of the protection board. Voltage clamping by series/antiparallel networks of 1N4448-equivalent switching diodes limits the gate voltage to ±0.7V and the drain voltage to between -0.7 and 2.1V. The LNAs (and other components that pass connections through to the outside) are wired to a single 25-pin microminiature D-connector on the board, which in turn is soldered directly to the filtered feedthru plate. There is a single protection board installed in the 1mm cartridge, which can accommodate two 3-stage C-band LNAs. The 3mm cartridge requires two boards, one for each 6-stage W-band LNAs.
 

The InP LNA Protection board is purely a passive circuit, and requires no power supplies. Physical size of the board (without connectors) is 32 x 48 mm.
 
 
 

3.0 Bias & Control Module Hardware
 

The ALMA Bias & Control Module (MOD2) is a 2-wide plug-in module within the ALMA Evaluation Receiver Electronics Bin (BIN2), a standard CSIRO AT-style 5U-high rack. The module provides DC bias voltages and currents for all components within the receiver cartridges (InP LNAs, SIS mixer bias electronics, Schottky diode mixers), with the exception of the temperature sensors. It also provides analog and digital monitor and control functions for these components, and for the Chopper and IF Module (MOD3). User access to these functions is via a remote host computer over the CAN bus interface; the protocol for these commands is described in a separate document [2].
 

The module contains six PCBs: a quad LNA bias card, dual Schottky mixer bias card, dual SIS superconducting magnet bias card, DC regulator board, analog I/O expansion card, and an embedded controller with a CAN bus interface ('AMBSI1-M'). A detailed hardware description of each is provided in the sections below.
 

The photo in Figure 5 shows the left and right side views of the module interior. Boards with fast digital circuitry (AMBSI1-M, Analog I/O board) and the DC regulator board are on one side, and the bias cards are on the other side. Interconnects between the two compartments are through a pair of 40-pin filtered connectors, to minimize coupled noise into the analog bias electronics. All module wiring (schematic) is to mating connectors, for quick board replacement if necessary. A front panel pushbutton switch is for momentary activation of the LEDs on all cooled InP amplifiers.
 

3.1 General Specifications
 

DC Power Requirements: +20V @ 400mA, -20V @ 130mA, +9V @ 650mA
 

Mechanical: AT-style blind mate 2-wide module; see Appendix B for drawings.
 

Backplane Connectors: 3 x 50-pin 'D' (device I/O, DC power); 9-pin 'D' (CAN)
 

Front Panel Monitors: None
 

Remote Interface: CAN bus
 

3.2 Quad LNA Bias Card
 

The ALMA Quad LNA Bias card (schematic : parts list) provides programmable DC bias for two 5-stage and two 3-stage Indium Phosphide HEMT amplifiers, along with multiplexed analog monitor outputs of FET drain voltage (V_ds), current (I_ds) and gate voltage (V_gs), on a compact Eurocard 3U board (100 x 160 mm). It is evolved from the CSIRO F60, a quad 3-stage design on a 6U card. As in the F60 (and earlier designs by NRAO and IRAM), V_ds and I_ds can be independently set, and the current stabilized by a servo loop that continuously adjusts V_gs. Two features unique to the F60 were retained in the current design:
 

• Drain current limit circuit. Limits output current to 20mA, for enhanced LNA protection. Adds 4 resistors and a PNP transistor to each stage.

 
• Sequenced, timed on/off of V_ds, I_ds and V_gs during power cycling or toggling of the ENAB line (enable/disable amplifier bias). During power-up/enable, V_g is applied first, followed by V_d and lastly I_d, over ~55 mS. The sequence is reversed on power-down/disable, but over a much shorter (~1.4 mS) interval.

 

As described above, there are three 16:1 analog multiplexers, one for each of the FET monitors, and the four select bits on each MUX are bussed together. Additionally, each amplifier has a separate enable bit. At power-up, or if any of the four on-board supply voltages are more than 10% under nominal, all eight bits are cleared, resetting the selected analog monitor to LNA1 Stage 1 and disabling bias to all four amplifiers. All eight bits are programmed over the same synchronous serial interface used for programming the DAC, using a separate enable bit (SYNC1). Hardware timing for the serial interface is given in Figure 6. Details on programming the DAC and enable/select bits, and reading the selected analog monitors are covered in the programming section of this document.
 

The LNA Bias card requires a regulated ±15V supply. Nominal quiescent current draw (zero amplifier bias) is 150mA and 46mA for the positive and negative supplies, respectively. All external connections (including power) are via a single DIN 41612 Type C 64-pin plug, which allows installation in a 3U subrack for other applications, if desired. Photographs of the front and back side of an assembled board are shown in Figure 7.
 

3.3 Dual Schottky Mixer Bias Card
 

The ALMA Dual Schottky Mixer Bias card (schematic : parts list) provides programmable tracking bipolar (0 to ±14.5V) DC bias for two cooled W-band Schottky mixers (Spacek M100-18LB). A single analog input (0 to 5V) on each mixer bias circuit is used to program the output voltages. Outputs are zener-clamped at 15V, to prevent damage to the mixers from overvoltage or polarity reversal. The measured current draw on each supply for both mixers is provided through four analog monitor outputs. Each current monitor has a nulling pot, to zero out any residual voltage offset from the monitor circuit, and is set with the bias outputs open-circuited and at full scale. Details on monitor and control of the card are covered in the programming section of this document.
 

A photograph of the assembled board is shown in Figure 8. Three single-row headers provide connections for power input, mixer output, and analog monitor/control. Except for the connectors, all components are surface mount, for a very compact board size (51 x 76 mm).
 

The Schottky Mixer Bias card requires a regulated ±15V supply. Nominal quiescent current consumption (zero mixer bias) is 3mA on each supply; at full bias, this increases to 13mA.
 

3.4 Dual SIS Magnet Bias Card
 

The ALMA Dual SIS Magnet Bias card (schematic : parts list) provides a programmable, high-current output drive for two superconducting magnet coils, used to suppress Josephson oscillations in the SIS mixer junctions. A single analog input (0 to 10V) on each bias circuit sets the coil drive current from 0 to 300mA. The output driver is a classic op-amp current source, using a current-sense resistor in a feedback loop and an N-channel power MOSFET as the output stage. A buffered current monitor output is also provided. Details on monitor and control of the card are covered in the programming section of this document.
 

The SIS Magnet Bias card requires a regulated ±15V supply for the control/monitoring circuits, and +5V for the output driver. Maximum current draw on these supplies is 2mA and 600mA, respectively (both circuits); since the Evaluation Receiver uses only one SIS mixer, the actual current draw is half the above.
 

The assembled board is shown in Figure 9. Three single-row headers provide connections for power input, mixer output, and analog monitor/control. Overall board size is 76 x 64 mm.
 

3.5 DC Regulator Card
 

The DC Regulator card (schematic) regulates the ±20V and +9V inputs from the Receiver Power Supply Bin down to the various voltages required by the bias electronics subsystem. Six connectors (J2-J7) provide DC power to the other boards in the Bias & Control Module, the Dual SIS Mixer Bias card in the 1mm receiver cartridge, and the LEDs used in the 3mm and 1mm InP LNAs. There are no monitor or control points on this board.
 

3.6 Analog I/O Card
 

The ALMA Analog I/O card (schematic : parts list) is a general-purpose precision analog interface board, designed to expand the analog I/O capability of the ALMA AMBSI1 embedded controller. Listed below are its principal features:
 

• 8 single-ended analog output channels, ±10V FS range, 14-bit resolution, 31µS settling time.
• 16 single-ended multiplexed analog inputs, ±10V FS range, 16-bit resolution, 100 kSPS.
• Parallel bus interface to AMBSI1, via expansion bus connector (50-pin ribbon cable)
• Power requirements: +15V @ 38mA, -15V @ 26mA, +5V @ 50mA

• Board dimensions: 89 x 89 mm.

 

Analog data acquisition is performed by a sequence of processor read/write cycles from the embedded controller to the board over the parallel bus. This is covered in the programming section of this document.
 

A photograph of the assembled board is shown in Figure 10. Two dual-row right-angle headers (J4, J3) provide external connection to the AMBSI1 expansion bus port and for analog I/O lines, respectively. The CPLD is programmed in-situ after board assembly via the 5-pin JTAG port (J1). DC Power to the board is through a 6-pin right-angle header connector (J5). Important note: This board can be damaged by improper sequencing of the power supplies. Always apply the logic supply (+5V) simultaneous with or after the ±15V; the logic supply should always be powered down first.
 

3.7 AMBSI1-M Embedded Controller Card
 

The ALMA Monitor and Control Bus Standard Interface, Type 1 ('AMBSI1') is a general-purpose 16-bit microcontroller board, designed to provide embedded control functions for ALMA receiver, LO and backend systems, and allow monitor and control of these from a host computer via the CAN bus. A detailed hardware description of the AMBSI1, including bus timing diagrams, can be found in [3]. There are two varieties available: the first (-M) is designed for embedded use in a module, and is the one used in the ALMA Bias & Control Module; the second (-B) is designed for use in a Eurocard 3U-high subrack, and integrates all I/O and power pins on a single 96-pin DIN connector. However, both varieties are the same physical size (100 x 160 mm). A photograph of an assembled board (AMBSI1-M) is shown in Figure 11.
 

In the receiver bias subsystem, the AMBSI1-M board controls data acquisition and output in the Analog I/O card via its external device bus, bias set/enable and monitor select functions in the Quad LNA Bias card via its synchronous serial interface and parallel I/O bits, and scaling of analog monitor and control data for all four bias cards. It also provides monitor and control functions for the Chopper and IF Module, which are outside the scope of this document. Detailed information on programming the controller for the above functions is given in the following section.
 
 
 

4.0 Embedded Controller Programming
 

This section describes the low-level I/O operations from the AMBSI1 necessary for interface to the bias electronics. Since the majority of interface signals are analog, the details of performing analog data acquisition and control with the Analog I/O card will be covered first, and are the basis for all analog monitor and control functions to the bias electronics. Digital I/O functions use the parallel I/O bits and the synchronous serial port of the microcontroller; implementation is described in [3].
 

4.1 Analog I/O Card
 

The Analog I/O card has internal registers and strobes that are mapped into the external device address range (base address 0x400000) of the AMBSI1 controller, and are used to control or monitor on-board devices. Table 1 shows the relative addresses of the registers and strobes, their functions, and where applicable, the corresponding signal name(s) on the card.
 

Notes:

¹ Byte addresses; all are on 16-bit word boundaries, with low byte stored first.

² All signals are 5V TTL compatible.

³ All eight DAC outputs are affected by this control bit; is cleared at power-up.

⁴ DAC_OUTx = 10 × ( Data / 2¹³ - 1) Volts. Mask bits b15..14 before converting to volts.
 

The default configuration of the AMBSI1 external bus interface is used, with one modification: for proper interface timing to the Analog I/O card, the parameter MTTC must be set for one memory tri-state wait state. This can be done during initialization of the AMBSI1.
 

4.1.1 Analog Input Procedure
 

To acquire data from one of the 16 analog inputs ADC_INx, the procedure is as follows:
 

• Select the desired analog input channel by writing to IN_SEL bits, as shown in Table 1.
• If value of IN_SEL has changed, wait at least 2 uS for analog input at A/D converter to settle.
• Initiate a conversion cycle on the A/D (/CONVERT strobe - see Table 1).¹
• Read the conversion data from the A/D (/RD_ADC); read cycle is extended until conversion is complete (~10 uS).
• Convert the signed binary integer to volts (1 bit = 305.176 uV).

4.1.2 Analog Output Procedure
 

To send data to one of the 8 analog outputs DAC_OUTx, the procedure is as follows:
 

• Convert desired DAC output voltage to corresponding offset binary code.²
• Write the output data to the desired DAC address, as shown in Table 1.³

Notes:

¹ 50 nS min. convert pulse width guaranteed for write cycles with at least 1 one state (default=7).

² Data = 2¹³ × ((V_OUT÷10) + 1)

³ Max. update rate for individual DAC is 31 uS.
 

4.1.3 Board Initialization
 

At power up, all eight DAC outputs are disabled (0V). However, the internal registers of the AD7841 DAC chip are undefined, and could go to random values when outputs enabled. To prevent this, the following steps are required after power-on:
 

• Write the data 0x2000 (0 Volts) to each DAC address.
• Enable the DAC outputs by setting the DAC Output Enable bit (see Table 1).

 

The Dual SIS Mixer Bias card requires two analog monitor inputs (V_{J_MON}, I_{J_MON}) and one analog control output (V_{J_SET}) per mixer channel, for a total of four inputs and two outputs. Table 2 shows the DAC and A/D channels that correspond to these analog monitor and control signals, and unit conversion factors. No digital I/O lines are used for this card.
 

The junction monitors require a minimum of 150 uS to settle, after the junction voltage has been changed. This is important if a swept I-V curve of the SIS junction is taken.
 

Notes:

¹ The 1mm cartridge only has one mixer; however, hardware and software supports two channels.

² Raw voltage monitors from A/D are scaled by this factor to obtain monitor parameters, and visa-versa for the DAC channels.
 

4.2.1 Calibration/Zeroing
 

As was mentioned earlier, residual voltage offset errors within the card can be removed in software by the embedded controller. There are three software offsets per mixer circuit, two for the monitors and one for the control voltage. These are set to zero at power-up, and can be individually adjusted by the remote host computer.
 

The offsets values are determined by bench tests, adjusting V_SET until the true zero bias point on the junction is found, and are different for every card. These bipolar offset values are stored in parameter units (not volts), and are subtracted from the monitor values (after scaling) and the control (set) parameters, prior to scaling.
 

4.3 Dual Schottky Mixer Bias Card
 

The Dual Schottky Mixer Bias card requires two analog monitor inputs (+I_{J_MON}, -I_{J_MON}) and one analog control output (V_{J_SET}) per mixer channel, for a total of four inputs and two outputs. Table 3 shows the DAC and A/D channels that correspond to these analog monitor and control signals, and unit conversion factors. No digital I/O lines are used for this card. The junction monitors require a minimum of 150 uS to settle, after the junction voltages have been changed.
 

Notes:

¹ Raw voltage monitors from A/D are scaled by this factor to obtain monitor parameters, and visa-versa for the DAC channels.
 

4.4 Dual SIS Magnet Bias Card
 

The Dual SIS Magnet Bias card requires one analog control output (I_SET) and one analog monitor input (I_MON) per magnet coil. Table 4 shows the DAC and A/D channels that correspond to these analog monitor and control signals, and unit conversion factors. No digital I/O lines are used. The monitors can take as long as 5 seconds to settle when commanded to full-scale output.
 

Notes:

¹ The 1mm cartridge only has one mixer; however, hardware and software supports two channels.

² Raw voltage monitors from A/D are scaled by this factor to obtain monitor parameters, and visa-versa for the DAC channels.
 
 
 

4.5 Quad LNA Bias Card
 

The Quad LNA Bias card uses three A/D channels on the Analog I/O card for monitoring the drain voltage and current and gate voltage of each FET. However, for setting the drain voltages and currents, the bias card has its own 32-channel DAC which is programmed serially. Lastly, there are 8 digital control bits: a group of four is used to select which FET is to be monitored, and the remaining bits enable or disable biasing of entire amplifiers. These bits are also programmed serially. In the following sections, the software aspects of each of these interfaces is covered.
 

4.5.1 Analog Monitors
 

Table 5 defines the three analog monitors on each FET. The appropriate digital control word must be sent to select the desired FET to monitor (Note: On power-up, the Stage 1 FET on LNA1 is selected by default). Always allow at least 2 uS for the input on the A/D to settle after selecting another FET, before acquiring the data.
 

Notes:

¹ Raw voltage monitors from A/D are scaled by this factor to obtain monitor parameters, and visa-versa for the DAC channels.
 

4.5.2 DAC Control
 

To update one of its DAC channels, the AD5532 accepts a 24-bit serial word, transmitted synchronously by the embedded controller. Generation of the serial clock and data on the AMBSI1 is through the Synchronous Serial Interface (SSC) of the Infineon C167CR processor; see [4] for programming details. The following points apply to the SSC for proper generation of the timing:
 

• Because the C167 can send a maximum frame size of 16 bits, three consecutive 8-bit transfers can be done. However, the DAC requires exactly 24 bits per transfer. Bit definitions are given in Table 6.

 
• The SSC is configured as master (generates the serial clock SCLK).

• Data is sent most significant bit (MSB) first.

 
• Data is shifted out on the trailing edge of SCLK (latched in the DAC on the trailing edge).

 
• The serial clock idles 'High' between transfers (is 'Low' on the DAC clock input).

 
• The maximum clock frequency that the DAC can accept is 14 MHz; however, a much slower rate (e.g., 200 kHz) would be preferred to minimize RFI.

 
• There must be at least 400 nS between successive writes to the DAC.

 

Notes:

¹ A '1' in this bit loads the data into the Offset DAC, which allows a programmable negative offset to be applied to all 32 outputs. Only used during board initialization; normally set to 0 to enable addressing of the DAC channels.

² See Table 7 below for details. MSB=b18. These bits are ignored if b20=1 (Offset DAC selected).

³ Format is straight binary, range 0-3V on all DAC channels (including Offset DAC). Actual buffered outputs (AD5532-1) are: V_OUT = 3.52 × V_DAC - 2.52 × V_OFFS. Resolution (V_OUT) is 644.53 uV
 
 

Notes:

¹ LNAs 1 & 2 are on the 3mm RX cartridge, LNA 3 on the 1mm cartridge. LNA 4 is not installed.

² No scaling required for setting FET drain voltage V_DRAIN. For drain current programming, V_{ID_SET} (volts) = 0.16506 × I_DRAIN,mA.
 

4.5.3 Digital Control
 

The eight on-board digital control bits (FET monitor select, LNA enables) are written using the same serial interface as the DAC. Functions of the control bits are defined in Table 8. Setup of the SSC is also almost the same, with the following changes:
 

• Frame size is 8 bits, and is done in a single transfer by the SSC.

 
• The chip select line SYNC1 is used to enable the on-board shift register. This is implemented with a parallel I/O port line, as detailed in Table 9. SYNC2 remains inactive.

 

 
 
 

4.5.4 Board Initialization
 

At power-up, the Quad LNA bias card defaults to a safe state, with bias disabled on all LNAs, and all DAC registers cleared. To allow proper setting of the drain voltage and current over their full ranges, a negative offset (-2.00 V) must be programmed into the outputs. From Table 6, the value required for V_OFFS. = 793.65 mV, or 0x10EA in the Offset DAC register. Therefore the initialization process for this board directly after power-up is as follows:
 

• Write Offset DAC (b20=1) with data 0x10EA, for -2.00 V output offset.
• Set all drain voltages and currents to zero. The corresponding DAC register value would be 0xC1E, assuming the output offset above.
• Enable bias on all amplifiers.

 

VD_SET = ROUND ( 2¹⁴ × ( V_DRAIN + 2.00) ÷ 10.56 ) (1)
 

ID_SET = ROUND ( 2¹⁴ × ( 0.16506 × I_DRAIN,mA.+ 2.00) ÷ 10.56 ) (2)
 

where VD_SET and ID_SET are the DAC integer data values (bits b13..0 in Table 6).
 
 
 

5.0 References
 

[1] A.R. Kerr and D. Boyd, "The NRAO Type-2B 1-2 GHz SIS Bias-T", NRAO EDTN #173, February 1996.

[2] A. Vaccari et. al., "Interface Control Document, ATF Evalution Front End Bias and Control Module (DRAFT)", ALMA-41.05.02.00-70.35.00.00-B-ICD, August 2002

[3] M. Brooks, "ALMA Monitor and Control Bus AMBSI1 Standard Interface Design Description", ALMA-SW-0013, Rev. B, March 2002

[4] Infineon Technologies AG, C167CR Derivatives User's Manual, Ver. 3.1, March 2000